Optimizing Delay and Area in One-Bit And Two-Bit Data Error Correction Using CRC

Authors: Gireesha K, Thejaswini B M

DOI: https://doi.org/10.37082/IJIRMPS.v12.i4.231062

Short DOI: https://doi.org/gt76pt

Country: India

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Abstract: In digital communication and storage systems, ensuring data integrity is crucial for reliable performance. This paper examines how Cyclic Redundancy Check (CRC) mechanisms for correcting both one-bit and two-bits in data transmissions. While CRCs are traditionally employed for error correction, this study extends their utility by introducing methods for error correction, aiming to enhance data reliability. This presents a new approach that leverages CRC-based techniques to rectify, single-bit and double-bit errors within transmitted data streams. The suggested method combines encoding and decoding capabilities of CRC using the diagonal bits, parity bits and check bits. Demonstrating significant improvements in error resilience over standard CRC implementations. Experimental findings indicate the proposed techniques offer effective solutions for error correction, with a focus on optimizing performance and accuracy. This approach primarily emphasizes optimizing the area and latency associated with error correction. The work contributes to the advancement of reliable error correction frameworks, which can be integrated into various communication and storage systems to maintain data integrity and mitigate the effects of transmission errors.

Keywords: Cyclic Redundancy Check, error correction, parity bit, diagonal bit and data transmission.

Paper Id: 231062

Published On: 2024-08-29

Published In: Volume 12, Issue 4, July-August 2024

Cite This: Optimizing Delay and Area in One-Bit And Two-Bit Data Error Correction Using CRC - Gireesha K, Thejaswini B M - IJIRMPS Volume 12, Issue 4, July-August 2024. DOI 10.37082/IJIRMPS.v12.i4.231062

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