Design and Implementation of VLSI Architecture for Power and Area Efficient MAC using Modified Booth Algorithm and Hybrid Adder

Authors: Thakshak M P, Vijaya Prakash AM

DOI: https://doi.org/10.37082/IJIRMPS.v12.i4.231085

Short DOI: https://doi.org/gt76pp

Country: India

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Abstract: This paper presents an area and power-efficient Multiply-Accumulate (MAC) unit architecture that integrates a modified Booth multiplier with a 16-bit hybrid adder and pipeline methodology, along with a Conditional gating technique. The modified Booth multiplier minimizes the number of partial products, optimizing power. and area efficiency. The hybrid adder, combining a 4-bit carry select adder and a 28-bit carry look-ahead adder, efficiently accumulates partial products and performs addition operations. The pipeline methodology is used to further boost performance by dividing the multiplication and accumulation process into stages, enabling parallel execution and higher throughput. The Conditional gating technique significantly reduces power consumption by dynamically disabling inactive pipeline stages and functional units. The MAC unit is designed to handle 16-bit input operands and produces a 32-bit output product. This architecture achieves an optimal balance between area, power consumption, and performance, making it ideal for resource-constrained digital signal processing and computing applications.

Keywords: Power-efficient MAC unit, Modified Booth multiplier, Hybrid adder, Pipeline methodology, Conditional gating technique

Paper Id: 231085

Published On: 2024-08-29

Published In: Volume 12, Issue 4, July-August 2024

Cite This: Design and Implementation of VLSI Architecture for Power and Area Efficient MAC using Modified Booth Algorithm and Hybrid Adder - Thakshak M P, Vijaya Prakash AM - IJIRMPS Volume 12, Issue 4, July-August 2024. DOI 10.37082/IJIRMPS.v12.i4.231085

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