Design of CODEC Using VLSI Architecture for Efficient Communication

Authors: P.N.S. Krishna Mohan, Pavan Singarapu, P. Venkat Ram

DOI: https://doi.org/10.5281/zenodo.14208878

Short DOI: https://doi.org/g8rrfk

Country: India

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Abstract: Codec refers to coder-decoder, encoding and decoding play a vital role in networking, storage, data communication and wireless or radio communication systems. Thus, the hardware architecture of an encoding and decoding blocks becomes an attractive issue in designing. Very large-scale integration (VLSI) is one of the trending processes of integrating thousands of transistors together in a chip and its architecture provides better performance. When the VLSI architecture is involved in the coder design ,the system attains effective results in its parameters such as power consumption, speed and area occupied. In general, digital systems the Half Cycle Processing Model (HCPM) is totally different which is already existing for FMO/Manchester Codec. Through this model reduces number of transistor count and achieves 100% Hardware Utilization Rate, it induces one cycle latency between positive and negative half cycles.To resolve this problem, we are proposing a new coder design which is integrated with previous one to reduce the delay

Keywords: -

Paper Id: 231639

Published On: 2018-08-03

Published In: Volume 6, Issue 4, July-August 2018

Cite This: Design of CODEC Using VLSI Architecture for Efficient Communication - P.N.S. Krishna Mohan, Pavan Singarapu, P. Venkat Ram - IJIRMPS Volume 6, Issue 4, July-August 2018. DOI 10.5281/zenodo.14208878

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